1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor memory or the like and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Conventionally, a semiconductor memory, in particular, a dynamic random access memory (DRAM), has been manufactured by using laminate SOI (semiconductor on insulator) technique. FIGS. 1A to 1L show an example of manufacturing methods of the DRAM.
First, as shown in FIG. 1A, a photoresist layer 2 is formed selectively on a portion of a major surface of a silicon substrate 1 on which a switching MOS (metal-oxide semiconductor) transistor is to be formed later. Using this photoresist layer 2 as a mask, the other portion 3 of the silicon substrate 1 which corresponds to a device isolation region is etched away to a predetermined depth C (for example, about 80 to 100 nm), thereby forming a step or convex portion 4 with a height of about 80 to 100 nm on the principal surface of the substrate 1.
Next, as shown in FIG. 1B, the photoresist layer 2 is removed and an insulating film 5 such as an SiO.sub.2 film or the like is formed over the entire surface of the substrate 1. Then, the insulating film 5 is partially removed by patterning process by using a photoresist layer 6 as a mask. That is, a boundary portion 7 of the insulating film 5 which extends over the convex portion 4 of the principal surface of the substrate 1 and the other concave portion 3 is selectively etched away to thereby expose the substrate 1 at the boundary portion 7.
Next, as shown in FIG. 1C, after the photoresist layer 6 is removed, a first polycrystalline silicon film 8 is formed over the entire surface of the substrate 1 including the insulating film 5 so as to bury the boundary portion 7, and an insulating film 9 such as an SiO.sub.2 film or the like is further formed on the silicon film 8.
Then, the insulating film 9 and the polycrystalline silicon film 8 are partially removed by patterning process by using a photoresist layer (not illustrated) as a mask, so that as shown in FIG. 1D, a columnar portion 10 composed of the polycrystalline silicon film 8 and the insulating film 9 is formed so as to correspond to the shape of a capacitor which will be formed later at the position corresponding to the boundary portion 7.
Next, as shown in FIG. 1E, after a second polycrystalline silicon film 11 is formed over the entire surface of the insulating film 5 and the columnar portion 10, the second polycrystalline silicon film 11 is partially removed by anisotropic etching process, thereby forming side walls 11A made of the polycrystalline silicon 11 on the flanks of the columnar portion 10 as shown in FIG. 1F.
Next, as shown in FIG. 1G, only the insulating film 9 of the columnar portion 10 is selectively etched away by using a photoresist layer 12 as a mask. As a result, a capacitor electrode 24 is constituted by the first polycrystalline silicon film 8 connected to the substrate 1 and the second polycrystalline silicon film side wall 11A.
Next, as shown in FIG. 1H, a dielectric film 13 is formed by deposition on the surface of the capacitor electrode 24.
Next, as shown in FIG. 1I, a third polycrystalline silicon film 14 constituting an opposite or counter electrode is thickly formed so as to bury the capacitor electrode 24. Subsequently, the counter electrode 14 constituted by the polycrystalline silicon film is levelled by grinding to the position indicated by a one-dot-chain line 15.
Then, as shown in FIG. 1J, another silicon substrate 15 which constitutes a support substrate is laminated onto the levelled surface of the counter electrode 14.
Next, as shown in FIG. 1K, the silicon substrate 1 is ground from the rear surface or the other major surface thereof to such a level that the convex portion 4 is remained and the insulating film 5 at the device isolation region is exposed. Thus, a thin silicon film 16 of about 80 to 100 nm thickness is formed by the convex portion 4 on the level.
Next, as shown in FIG. 1L, a word line 19 serving as a gate electrode is formed on the thin silicon film 16 through a gate insulating film 18. Impurity is diffused in the thin silicon film 16 by using the word line 19 as a mask to thereby form diffusion regions 20, 21 and 22 constituting a source and a drain in the thin silicon film 16 so that a switching MOS transistor 23 is formed therein. A capacitor 25 is composed from the capacitor electrode 24, the dielectric film 13, and the counter electrode 14 made of the third polycrystalline silicon in which the capacitor 25 is connected to the diffusion regions 21 and 22.
As shown in FIG. 1L, after an insulating film 26 is formed, a contact hole 27 is formed and then a bit line 28 is formed so as to be connected to the diffusion region 20. As a consequence, a desired DRAM cell 29 is obtained which is constituted by the capacitor 25 for storing electric charges and the switching MOS transistor 23 for controlling the transferring and draining electric charges to and from the capacitor 25.
In such a conventional manufacturing method as mentioned above, however, it is difficult to leave the thin silicon film 16 in the grinding step of FIG. 1K. As mentioned above, the thickness of this thin silicon film 16 is about 100 nm. Consequently, in view of grinding irregularities, warpage of the semiconductor wafer, and unevenness in the thickness of the semiconductor wafer or the like, it is difficult to control the thickness of the thin silicon film 16 on the wafer surface. For example, if the grinding is carried out excessively in order to eliminate the irregularities of the thickness, the thin silicon film 16 will disappear.
Due to the fact that the thickness of the thin silicon film 16 is being further thinned to several tens of nm in accordance with improvements in the degree of integration, it is becoming increasingly difficult to leave the thin silicon film 16 by grinding it from the rear surface of the silicon substrate 1.